Skytone A700 CPU specs

According to Texet - one of the retailers that sells Skytone A700 as 8.9" Touch Screen Tablet PC (EZB890), the CPU is RMI AU 1250.

Its primary features are:

Customized MIPS32® Core

• 333, 400, and 500MHz

• 32-bit architecture

• 16KB instruct + 16KB data caches

• High-speed multiply-accumulate (MAC) and divide unit

• 1.2V core, 3.3V I/O

Media Acceleration Engine (MAE)

• Support for MPEG1, 2, 4, and WMV9 scaled up to 1024x768

• MPEG2 main profile/main level (720x480, 10Mbps, 30fps)

• MPEG4 advanced simple profile/level 5 (720x480, 4Mbps, 30fps)

• WMV9 main profile/medium level (720x480, 2.5Mbps, 30fps)

• DivX® certified portable

DDR SDRAM Controller

• Supports 2.5 or 1.8V DDR1/DDR2 and mobile DDR memory with speeds up to DDR500

• 16/32-bit data, 14-bit address

• Up to 512MB (four 1-Gbit devices)

• 1:1, 2:1, 3:1 system bus clock to memory clock options

• Unified memory architecture with dedicated video subsystem

Static Bus Controller

• 16-bit data bus interface

• IDE interface with support for PIO mode and multiword simple DMA data transfers

• Support for both NOR and NAND Flash devices

— Boot from NAND or NOR Flash

— Supports 30 bits of addressable memory using 15 pins and address latch protocol

• Compact Flash/PCMCIA

• Support for external 10/100 Ethernet controller

AES Hardware Encrypt/Decrypt Engine

• AES 128

• ECB, CBC, CFB, OFB modes supported

• 100/50/25/12MHz clock option for power/performance considerations

LCD Controller

• Up to 1024x768 resolution screens

• 32-bits per pixel aRGB color resolution support

• Four prioritizable overlay windows

• Alpha override and per-pixel alpha blending

• Four-color hardware cursor

• Configurable on-chip memory area for palette RAM, gamma correction, or 1KB frame buffer

Integrated Peripherals

• Two Programmable Serial Controllers (PSCs) – each independently capable of being programmed for AC97, I2S, SPI, and SMBus (system management bus) serial protocols

• Two Secure Digital/SDIO/MMC Controllers

• USB 2.0 Host and Device Controller with HS, FS, and LS support (for both)

— Configurable Host, Device, OTG (On-the-Go) support

• Two UARTs

• GPIO (48)

Camera Interface Module

• 8-10 bit parallel data bus

• Planar modes support CMOS/CCD sensors

• CCIR 656 data input

• CIM image data is autonomously planarized in RGB or YCbCr format, relieving the core from the actual work

• A Raw Data Mode supports moving CIM input data unchanged to memory

Power Management Modes

• Sleep

• Hibernate

• Idle0/Idle1

Other

• Low power

• Package: Pin count 372 Plastic BGA